Leakage control during circuit operation is more challenging than standby mode control due to the short time to deactivate blocks, large overhead energy and run-time leakage variations. This paper proposes circuit techniques that address these challenges to reduce run-time leakage in on-die SRAM caches. A source-biased gated-ground SRAM is proposed; an efficient way to utilize this technique un...

Due to Technology scaling the importance of leakage power has significantly increased in the modern day system-on-chip devices. The runtime leakage component during the active state is almost becoming equal to the standby leakage component. Hence Present day research is more focused on reduction of runtime leakage current .we present a novel runtime leakage reduction for 70nm technology. As an ...

We develop a new notion of security against timing attacks where the attacker is able to simultaneously observe the execution time of a program and the probability of the values of low variables. We then show how to measure the security of a program with respect to this notion via a computable estimate of the timing leakage and use this estimate for cost optimisation.

Graphics Processing Units (GPUs) maintain a large register file to increase thread block occupancy, hence to improve the thread level parallelism (TLP). However, register files in the GPU dissipate a significant portion of the total leakage power. Leakage power of the register file can be reduced by putting the registers into low power (SLEEP or OFF) state. However, one challenge in doing so is...

A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI circuit has become a major constrain in a battery operated device for technology node below 90nm, as it drains the battery even when a circuit is in standby mode. Major concern is the leak...

In this paper, we study the interdependencies between system’s leakage and on-chip temperature. We show that the temperature variation caused by on-chip heat accumulation has a large impact in estimating the system’s leakage energy. More importantly, we propose an online temperature-aware leakage minimization technique to demonstrate how to incorporate the temperature information to reduce ener...

Bellman’s optimality principle is a method for solving problems where one needs to find best decisions one after another. The principle can be extended to assess the information leakage in multi-threaded programs, and is formalized into the optimum leakage principle hereby proposed in this paper. By modeling the state transitions in multithreaded programs, the principle is combined with informa...

objectives: microleakage is the main concern in composite restorations. this study aimed to compare the microleakage of two bulk-fill and one conventional composite at two different time points. methods: class ii cavities were prepared in 60 premolar teeth and divided into six groups of 20. groups 1 and 4 were incrementally filled with grandio composite. groups 2 and 5 were filled with x-tra fi...

Because of its wide applicability, many eecient implementations of the Fast Fourier Transform have been developed. We propose that an eecient implementation can be produced automatically and reliably by partial evaluation. Partial evaluation of an unoptimized implementation produces a speedup of over 9 times. The automatically generated result of partial evaluation has performance comparable to...

This report surveys progress in the field of designing low power especially low leakage CMOS circuits in deep submicron era. The leakage mechanism and various recently proposed run time leakage reduction techniques are presented. Two designs from Cadence and Sony respectively, which can represent current industrial application of these techniques, are also illustrated. 1 The work behind this re...